1. Field of the Invention
The invention relates to a gate array integrated circuit, forming part of a semiconductor integrated circuit, and a layout method for a gate array integrated circuit.
2. Description of the Background Art
Traditionally, a gate array is composed of basic functional cells, such as inverters and flip-flops. A basic functional cell is implemented by optionally designing the wiring pattern layer of a unit cell. As shown in FIG. 11, for example, a specific layout of a unit cell 400 is defined by a basic layer which has a p-type metal-oxide-semiconductor (PMOS) transistor 402 and an n-type metal-oxide-semiconductor (NMOS) transistor 404 interconnected to each other by strips of poly-crystalline silicon 406 and 408. The PMOS transistor 402 may consist of an n-type well 410, a p-type implantation layer 412, an active region 414 and a p-type layer 416 The NMOS transistor 404 may consist of a p-type implantation layer 418, an active region 420 and an n-type layer 422.
The basic layer of the unit cell 400 is overlaid with an upper wiring pattern layer which includes, e.g. contact pads 434 and a first layer of metal strips 436, etc., FIG. 12, to form the wiring layer, a dual-input NAND gate 430 being thus laid out to serve as a basic functional cell.
Usually, a unit cell conveys information on terminals functioning as nodes for connecting basic functional cells with each other. Specifically, the dual-input NAND gate 430 has plural gate terminals 432. In order to optimize the size of the cells, each of the plural gate terminal regions 432 has its size suitable for accommodating therein the single contact pad 434 or a single through-hole for connecting transistors or basic functional cells. Further, as seen from FIG. 12, desired ones of the plural gate terminal regions 432 are provided with input terminals a and b, and the first layer of metal strips 436 has an output terminal yn provided at a desired position.
Japanese patent laid-open publication No. 321559/1996 discloses a polycide gate electrode structure formed in a hook-like shape in a unit cell of static random-access memory (SRAM). In the structure, the polycide wiring pad for contact with wiring metal and the polycide wiring strip to the branching point of the polycide gate are of n-type polycide. It is thus possible to suppress the variety of the threshold, Vth, of the n-channel transistor caused by boron, B, diffused in the lateral direction in the dual polycide gate electrode region.
Further, Japanese patent laid-open publication No. 8441/1996 discloses a dual gate type of field effect transistor, in which the first gate electrode has plural power-fed points and the second gate electrode has a single power-fed point, so that the first gate electrode is of a comb-like gate structure and the second gate electrode not of a comb-like gate structure. That makes it possible not to lay out the second gate and drain electrodes, across which the highest voltage is applied while the transistor is operative, so as not to cross each other.
Furthermore, Japanese patent laid-open publication No. 307447/1995 discloses as a technology of a basic cell for a gate cell a semiconductor device having its gate electrode turning and a semiconductor device having its gate electrode rectangularly turning several times.
For manufacturing gate arrays, improvement is always required in micro-miniaturization and yield. With the conventional gate arrays as well as the Japanese patent publications described above, however, each of the gate electrode regions has its contact pad or through-hole disposed in single sit. That made it difficult to accomplish the improvement as required in micro-miniaturization and yield.